Gate-Side Hydrogen Regulation by an In-Situ NiO Interlayer in ITO FETs Achieving Sub-5 mV ΔVTH @ 1 ks under EOX of 5 MV/cm and 415 K
通过栅侧界面工程调控氢相关不稳定性。Gate-side interface engineering for hydrogen-related instability.
NUS / Electrical & Computer Engineering
博士候选人
氧化物半导体器件与可靠性Ph.D. candidate
Oxide semiconductor devices & reliability
01 / 05 · 从哪里开始
蓝色是底层硅器件,金属线把器件连成电路。现在的问题是:能不能利用它上方的空间?
n 型 · 固定 Vᴅ · 归一化,仅改变阈值的教学模型。Iᴅ,₀ 为固定 Vɢ 处的初始电流;实际 Iᴅ 也受迁移率、接触等因素影响。n-type · Fixed Vᴅ · Normalized threshold-only teaching model. Iᴅ,₀ is the initial current at the fixed Vɢ. Real Iᴅ also depends on mobility, contacts and other factors. 模型背景 ↗Model background ↗
从硅电路到上层氧化物器件,放大介绍材料与界面研究,再回到三维集成。结构、曲线与高亮仅用于解释概念,非实际比例或工艺流程;不同研究方向不代表一套已完成的集成工艺。From silicon circuits to upper-tier oxide devices, then into materials and interfaces, and back to 3D integration. Geometry, curves and highlights are conceptual, not to scale or a process flow. Research directions are not a demonstrated integrated process. imec: M3D ↗
通过栅侧界面工程调控氢相关不稳定性。Gate-side interface engineering for hydrogen-related instability.
研究氟处理器件的可靠性及宽温区行为。Reliability and wide-temperature behavior of fluorine-treated devices.
通过室温氟化调控器件阈值,并验证高增益反相器。Room-temperature fluorination for threshold control and high-gain inverter demonstrations.
以上三项以研究主题介绍,链接指向正式论文。* 表示共同贡献。These three entries are research-theme summaries linked to the published papers. * Equal contribution.
我研究氧化物晶体管,
尤其关心它们为什么会变得不稳定,
以及怎样让它们更可靠。I study oxide transistors—
why they become unstable,
and how to make them more reliable.
在 NUS,我从器件制备与电学测试出发,研究缺陷、氢与栅侧界面对稳定性的影响。目前的工作主要围绕氟钝化、界面工程,以及后道兼容器件的阈值调控。At NUS, I combine device fabrication and electrical measurements to study how defects, hydrogen, and gate-side interfaces affect stability. My work focuses on fluorine passivation, interface engineering, and threshold control in BEOL-compatible devices.
从材料与界面,到器件的实际表现。From materials and interfaces to device behavior.
偏压和温度应力下,晶体管的阈值为什么会漂移?我研究氟钝化与栅侧界面工程如何影响这些退化过程。Why does transistor threshold voltage drift under bias and temperature stress? I study how fluorine passivation and gate-side interface engineering affect these degradation processes.
后道集成不能依赖高温处理。我研究用室温氟化调节器件阈值,并通过反相器验证它在逻辑电路中的应用。BEOL integration limits the thermal budget. I investigate room-temperature fluorination for threshold control, with inverter demonstrations connecting device engineering to logic circuits.
合作研究还涉及氧化物器件的短沟道效应与存储应用:My collaborative work also examines short-channel effects and oxide memory: 区分偏压应力效应与真实 DIBLdistinguishing bias-stress artifacts from intrinsic DIBL。
我的研究从洁净室里的器件制备开始,接着是电学与材料表征,再回到数据和器件物理。My research starts with cleanroom fabrication, continues through electrical and materials characterization, and returns to data and device physics.
除了研究,我也是 NUS E6 洁净室的设备高级用户,参与操作规范编写与新用户培训,并担任 IEEE Electron Device Letters 审稿人。I am also a designated tool superuser in the NUS E6 cleanroom, contributing to operating procedures and new-user training, and a reviewer for IEEE Electron Device Letters.
EBL · ICP-RIE · ALD · Sputtering
XPS · SIMS · TCAD · Python · MATLAB
2020 MCM · Meritorious Winner
National University of Singapore电气与计算机工程 · 博士在读Ph.D. candidate, Electrical & Computer Engineering预计 2027 年 2 月毕业Expected graduation: February 2027
National University of Singapore电气工程 · 硕士M.Sc., Electrical Engineering
华南理工大学South China University of Technology信息工程 · 学士B.Eng., Information Engineering
研究合作、器件与工艺研发,或职业机会。Research collaboration, device and process R&D, or career opportunities.