我致力于提升后道工艺（BEOL）兼容氧化物半导体的稳定性，为下一代三维集成提供可靠的器件基础。围绕这一植根于材料本性的关键挑战，我研究缺陷与界面的物理机制，并探索面向新型逻辑与存储的解决路径。I work on making BEOL-compatible oxide semiconductors reliable for next-generation three-dimensional integration. My research addresses stability challenges rooted in the material’s electronic structure and defect physics, developing routes toward dependable logic and memory.
新加坡Singapore预计 2027 年 2 月毕业Expected graduation · Feb 2027
学术会议与期刊CONFERENCES & JOURNALS
IEDM
VLSI Symposium
IEEE EDL
IEEE TED
从芯片走进器件FROM CHIP TO DEVICE
M3D：让芯片向上生长M3D: building upward
从硅基底层器件，到后道兼容的氧化物器件，再到上下协同的完整结构。沿着芯片的垂直方向，看见我的研究所在。From silicon devices to BEOL-compatible oxide transistors and a connected stack. Follow the chip’s vertical dimension to see where my research fits.
CHIP → FEOL → BEOL → M3D
CHIP
从一颗芯片开始Inside the chip
走进芯片内部，观察器件与互连如何向垂直空间延伸。Look beneath the surface to see how devices and connections extend into the vertical dimension.
动画依次展示：一颗芯片；硅衬底上的 FEOL CMOS 器件；在已有电路上方集成的 BEOL 兼容氧化物器件；以及由垂直互连连接的 M3D 结构。氧化物器件的稳定性是我的研究重点。The animation shows a chip, FEOL CMOS devices on a silicon substrate, BEOL-compatible oxide devices above existing circuitry, and the M3D stack linked by vertical connections. Oxide-device stability is the focus of my research.
一种后道兼容氧化物 M3D 路线的概念示意。剖面与层次展示经过简化，非实际器件比例或完整工艺流程。Conceptual illustration of one BEOL-compatible oxide M3D route. The cutaway and tier reveal are simplified, not to scale or a complete fabrication sequence.
低温制造与低漏电，让氧化物半导体成为延续摩尔定律、发展单片三维集成的重要候选。我的工作聚焦其走向应用必须面对的稳定性与器件控制问题。Low-temperature processing and low leakage make oxide semiconductors promising for monolithic three-dimensional integration and continued scaling. I focus on the stability and device control needed to turn that promise into practical technology.
稳定性挑战与材料的电子结构、缺陷和氢行为密切相关。我通过氟钝化与栅侧界面工程，识别并调控不同退化机制，为氧化物器件的可靠运行提供物理依据与工艺路径。Stability is closely linked to electronic structure, defects, and hydrogen behavior. Through fluorine passivation and gate-side interface engineering, I identify and control degradation mechanisms, establishing physical insight and process routes for reliable operation.
为三维集成中的长期可靠运行奠定基础。A foundation for dependable operation in three-dimensional integration.
从有潜力的材料， 走向可用的电路。From promising materials to functional circuits.
后道集成要求在有限的热预算下实现可控的器件特性。我开发室温氟化方法调节晶体管工作状态，并通过反相器验证，为氧化物半导体构建实用逻辑电路提供工艺路径。BEOL integration calls for controllable devices within a limited thermal budget. I develop room-temperature fluorination to tune transistor operation and validate it in inverters, providing a process route toward practical oxide logic.
连接材料工程与后道兼容逻辑电路。Connecting materials engineering with BEOL-compatible logic.
器件测试中的表观现象，会影响对微缩潜力与数据保持能力的判断。在合作研究中，我们区分偏压应力引起的测量效应与真实短沟道行为，为氧化物存储器的设计与评估提供更准确的物理图景。Apparent device behavior can obscure scaling potential and data retention. In collaborative work, we distinguish bias-stress measurement effects from intrinsic short-channel behavior, giving oxide memory design and evaluation a clearer physical foundation.
让存储器设计建立在正确的器件物理之上。Grounding memory design in the right device physics.
最新工作获 IEDM 2026 接收，尚未正式发表。此前成果发表于 VLSI Symposium、IEEE EDL 与 TED，包括 VLSI 第一作者及共同第一作者工作。以下展示与研究主线相关的代表成果。My latest work has been accepted for IEDM 2026 and is not yet published. Earlier contributions appeared at the VLSI Symposium and in IEEE EDL and TED, including first- and co-first-author VLSI work. Selected contributions to these research themes are highlighted below.
2026
IEEE International Electron Devices Meeting (IEDM)第一作者First author已接收 · 待发表Accepted · Forthcoming
以上以研究主题介绍成果；IEDM 2026 条目仅依据会议官网公开摘要，链接至摘要页面，其余条目链接论文原文。* 表示共同贡献。Contributions are introduced by research theme. The IEDM 2026 entry draws only on the public conference abstract and links to that page; other entries link to the published papers. * Equal contribution.
关于我ABOUT
研究背景与实践Background & practice
目前在新加坡国立大学攻读电气与计算机工程博士学位。我的工作贯穿洁净室器件制备、电学与材料表征，以及基于物理机制的数据分析。I am a Ph.D. candidate in Electrical and Computer Engineering at NUS. My work spans cleanroom fabrication, electrical and materials characterization, and physics-based data analysis.
在 NUS E6 洁净室担任设备高级用户，参与操作规范编写和新用户培训；同时担任 IEEE Electron Device Letters 审稿人。As a designated tool superuser in the NUS E6 cleanroom, I contribute to operating procedures and new-user training. I also serve as a reviewer for IEEE Electron Device Letters.